DK-DEV-5SGXEA7N【PDF 19/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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1-10

Arithmetic Mode

SV51002

2014.01.10

Arithmetic Mode

The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two dedicated full adders.

The dedicated adders allow the LUTs to perform pre-adder logic; therefore, each adder can add the output

of two 4-input functions.

The ALM supports simultaneous use of the adder ’ s carry output along with combinational logic outputs.

The adder output is ignored in this operation.

Using the adder with the combinational logic output provides resource savings of up to 50% for functions

that can use this mode.

Arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and

subtract control, synchronous clear, and synchronous load.

The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up/down,

and add/subtract control signals. These control signals are good candidates for the inputs that are shared

between the four LUTs in the ALM.

The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the

LAB. You can individually disable or enable these signals for each register. The Quartus II software

automatically places any registers that are not used by the counter into other LABs.

Figure 1-11: ALM in Arithmetic Mode for Stratix V Devices

datae0

4-Input

carry_in

adder0

LUT

dataf0

datac

datab

dataa

4-Input

LUT

reg0

datad

4-Input

LUT

adder1

reg1

To General or

Local Routing

datae1

4-Input

reg2

dataf1

LUT

carry_out

reg3

Carry Chain

The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic

mode.

The two-bit carry select feature in Stratix V devices halves the propagation delay of carry chains within the

ALM. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal

is routed to an ALM, where it is fed to local, row, or column interconnects.

To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is

implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB

Altera Corporation

Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices

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